1. Technical Field of the Invention
The present invention relates to the field of memory transfers in digital computers, and more particularly, to a direct memory access controller that provides a plurality of direct memory access channels over which memory data can be transferred.
2. Description of Related Art
In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself.
In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.
A commercially available DMA controller is the 8237 DMA controller manufactured by Intel. Each 8237 DMA controller provides four separate DMA channels which can be used independently for memory transfers. Certain well-known computer systems, such as the IBM PC/AT design, contain two 8237 DMA controllers. One channel of the DMA controllers is used to cascade the second DMA controller. The pair of DMA controllers therefore provide a total of seven DMA channels, with four channels provided by the first controller, and three channels provided by the second controller.
Each of the seven DMA channels has the capability of providing 16-bit accesses to memory. The channels are also configurable to provide 8-bit accesses to memory. Whether a channel forms 16-bit accesses or 8-bit accesses is dependent upon on which controller a channel is located. In this prior art system the hard-wiring of the controller chip to the address lines of the address bus determines whether the channels of that particular DMA controller chip would form 16-bit accesses or 8-bit accesses to memory. Once the DMA controller chips are connected to the address bus, all of the DMA channels of a controller chip are set to provide the same size access to memory as the other DMA channels on that chip. In the PC/AT design, the four channels 0-3 contained on the first DMA controller chip are defined as 8-bit channels, while the three DMA channels 5-7 on the second DMA controller chip are defined as 16-bit channels. Channel 4, located on the second DMA controller chip, is the cascade channel which allows channels 0-3 of the first DMA controller to arbitrate through the priority network of the second DMA controller.
In order to provide the differently sized memory accesses, the address connections of the first DMA controller to the address bus in the PC/AT are different than the address connection of the second DMA controller to the address bus. This connection allows the first DMA controller channels to perform even or odd accesses and therefore 8-bit accesses to memory. The second DMA controller is connected to the same address bus as the first DMA controller, but in a shifted manner which causes the second DMA controller to perform only even address or 16-bit accesses to memory. The second DMA controller therefore will only be able to perform word transfers, while the first DMA controller performs byte transfers.
The hard-wired configuration of the interface between the cascaded DMA controllers and the address bus limits the PC/AT computer system to four 8-bit DMA channels and three 16-bit DMA channels. This constrains the system designer in the number of 8-bit and 16-bit slaves that can be coupled to the system.